Field of the Art
The disclosure relates to the field of semiconductors, and more particularly to the manufacture and testing of semiconductors with complex conductive structures.
Discussion of the State of the Art
2.5-D and 3-D packaging is a novel implementation of an already well-established concept that previously was referred to as MCMs (multichip modules). A thin glass, silicon or other dielectric substrate material is created having a plurality of holes or vias that are metalized in such a manner as to create a connection between one circuit plane and a second circuit plane. The integrated circuit packaging industry refers to these interconnection substrates as interposers. Holes fabricated into the interposer are typically very small, for example, 5 μm to 100 μm in diameter and 50 μm to 500 μm in depth. The number of holes per square centimeter may be in the hundreds or even thousands. Following the processing necessary to fabricate these holes the next step is to metalize the hole to provide for an electrically conductive pathway from one circuit plane or substrate to another.
Current state of the art processes known as “copper electroplate” methods for metalizing interposer through and blind holes are very costly and lack manufacturing scalability. The metallization methods include a combination of pressure vapor deposition (PVD) or sputtering deposition to form a seed layer followed by copper electroplating. The sputtering or PVD methods along with very sophisticated copper electroplating operations are very costly in materials and operational expense and require highly trained technicians to operate the process. The equipment necessary to run these processes is extremely expensive and difficult to scale to high-throughput manufacturing. The copper electroplating process takes 1 to 8 hours for each substrate, depending on hole diameter and aspect ratio. The electroplating process requires each substrate to be electroplated in an individual process cell having sophisticated analytical and dispensing controls and precision electrical field distribution across the substrate.
Electroplated copper deposits extending beyond the surface of the substrate are referred to in the art as “over burden”. To level the copper electroplate deposit flush or planar to the substrate surface requires a secondary process using chemical-mechanical polishing (CMP). Maintenance and operation of the CMP process requires highly skilled technicians for monitoring and control to achieve consistent results. Copper is a relatively soft metal and methods used to mechanically remove the excess copper are constrained by the loading of the soft copper into the abrasive material.
A second means of depositing copper or other conductive materials into via holes in interposer substrates utilizes metallic inks. The metallic inks typically are formulated using metal powder dispersed in a bonding resin or other polymer for ease of hole filling and a capping agent to prevent the metallic powder from oxidizing. After the holes are filled with the metallic ink along with the resin or capping agents it is necessary to volatize all organic materials and remove them from the metallic powder to achieve reasonable electrical conductivity. Temperatures required for volatizing these organic compounds may reach 400° C. to 500° C. The carbon ash left after volatizing the organic compounds may negatively impact optimal conductivity and leave significant potential for discontinuous filling of the hole. The potential for discontinuous or electrically open areas in the filled hole or via is unacceptable.
Most of these processes work only on a very limited hole length/width ratio, and narrow or extra wide holes are very difficult to manufacture in a consistent manner.
What is needed is a system and method whereby a silicon, glass or other dielectric or semiconductor substrate material having through or blind vias may be metalized with a highly conductive metal at very low operational or material cost and with limited requirements for highly trained technical personnel. The process is easily scaled and equipment costs are significantly less than all other process methods. The resulting metallization of the hole is electrically conductive (approaching that of bulk copper), is resistant to oxidation during thermal cycling tests, and has little to no potential for discontinuous or electrically open vias.
Also needed is the ability to manufacture a wide range of aspect ratios of the holes on one substrate, for example, to reach a required via density in a conduction area, as well as fill very wide holes as thermal transfers for cooling components mounted on said substrates/interposers.